Principal Memory Subsystem Engineer (Design or DV)

Microsoft

United States, California, Mountain View

Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Artificial Intelligence System on Chip (AISoC) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Principal Memory Subsystem Engineer (Design or DV) to join the team.
Responsibilities

Provide technical leadership for Memory Subsystem development as a Design or Design Verification (DV) engineer, driving solutions from architecture and microarchitecture through silicon bring-up.
Lead the design, integration, and verification of high-performance, complex SoC subsystems, with a focus on memory technologies, bandwidth, latency, utilization, power, and overall system efficiency.
Collaborate closely with Architecture, RTL Design, DV, Physical Design (PD), Design-for-Test (DFT), Firmware, and Post-Silicon teams to resolve system-level issues and deliver robust silicon.
Drive vertical and horizontal IP/component reuse across projects and platforms, ensuring scalable and efficient subsystem architectures.
Provide technical leadership through mentorship, design reviews, code reviews, and cross-functional collaboration, helping to establish and maintain engineering best practices.
Develop and optimize subsystem architectures involving PCIe, HBM, imaging and control subsystems, interconnect fabrics, AMBA AXI/CHI protocols, DMA engines, NoCs, and high-throughput data buffering and movement.
Drive design implementation, including microarchitecture specification, RTL development and integration using Verilog/SystemVerilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, lint, and RDC.
Lead verification activities, including development of verification strategies and test plans, UVM-based constrained-random environments, scoreboards, checkers, assertions, functional coverage, and coverage closure.
Debug complex design and system-level issues across simulation, emulation, and silicon, working across disciplines to identify root causes and implement effective solutions.
Drive execution in an Agile development environment, including sprint planning, feature deployment, code reviews, issue resolution, and continuous improvement of design and verification processes.
Champion high-quality engineering execution and contribute to delivering cutting-edge, custom IP and SoC solutions that meet demanding performance, power, efficiency, and schedule requirements.
Qualifications
Required/minimum qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Additional or Preferred Qualifications
Experience debugging Register Transfer Level (RTL) designs as well as simulation and/or emulation environments.
Experience with design quality and static checks, DFT implementation and hand off to physical design.
Expertise in design or DV domains
8+ years expertise in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure.
8+ years of experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug
9+ years of experience in either design and integration or DV with a proven track record of delivering high-performance IP, SS or SOC testbenches.
Experience with verification for multiple product cycles from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM).
5+ years experience with lead roles across cross-functional / cross-time-zone engineering teams.
Lead experience for an IP or SS related to CPUs, VPUs, GPUs, Direct Memory Access (DMA) engine, Tensor unit, or similar
Experience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs
Experience in Scripting language such as Python or Perl
Hands on experience in Formal property verification (DV)
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Principal Memory Subsystem Engineer (Design or DV)

Microsoft

United States, California, Mountain View

Provide technical leadership for Memory Subsystem development as a Design or Design Verification (DV) engineer, driving solutions from architecture and microarchitecture through silicon bring-up.
Lead the design, integration, and verification of high-performance, complex SoC subsystems, with a focus on memory technologies, bandwidth, latency, utilization, power, and overall system efficiency.
Collaborate closely with Architecture, RTL Design, DV, Physical Design (PD), Design-for-Test (DFT), Firmware, and Post-Silicon teams to resolve system-level issues and deliver robust silicon.
Drive vertical and horizontal IP/component reuse across projects and platforms, ensuring scalable and efficient subsystem architectures.
Provide technical leadership through mentorship, design reviews, code reviews, and cross-functional collaboration, helping to establish and maintain engineering best practices.
Develop and optimize subsystem architectures involving PCIe, HBM, imaging and control subsystems, interconnect fabrics, AMBA AXI/CHI protocols, DMA engines, NoCs, and high-throughput data buffering and movement.
Drive design implementation, including microarchitecture specification, RTL development and integration using Verilog/SystemVerilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, lint, and RDC.
Lead verification activities, including development of verification strategies and test plans, UVM-based constrained-random environments, scoreboards, checkers, assertions, functional coverage, and coverage closure.
Debug complex design and system-level issues across simulation, emulation, and silicon, working across disciplines to identify root causes and implement effective solutions.
Drive execution in an Agile development environment, including sprint planning, feature deployment, code reviews, issue resolution, and continuous improvement of design and verification processes.
Champion high-quality engineering execution and contribute to delivering cutting-edge, custom IP and SoC solutions that meet demanding performance, power, efficiency, and schedule requirements.
Qualifications
Required/minimum qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Additional or Preferred Qualifications
Experience debugging Register Transfer Level (RTL) designs as well as simulation and/or emulation environments.
Experience with design quality and static checks, DFT implementation and hand off to physical design.
Expertise in design or DV domains
8+ years expertise in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure.
8+ years of experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug
9+ years of experience in either design and integration or DV with a proven track record of delivering high-performance IP, SS or SOC testbenches.
Experience with verification for multiple product cycles from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM).
5+ years experience with lead roles across cross-functional / cross-time-zone engineering teams.
Lead experience for an IP or SS related to CPUs, VPUs, GPUs, Direct Memory Access (DMA) engine, Tensor unit, or similar
Experience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs
Experience in Scripting language such as Python or Perl
Hands on experience in Formal property verification (DV)
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.