Intel
US, Oregon, Hillsboro
Come join Intel Foundry's Silicon Technology Development (Si TD) Quality and Reliability organization as a Process Integration Development Engineer within the Integrated Quality and Reliability team. The Integrated QR team develops and executes integrated reliability methodologies, defect reliability assessments, HTOL/ELFR certification strategies, ELF modeling, and MTS quality systems that enable technology certification for Intel Foundry's leading-edge process technologies. The team partners closely with technology development, design, test and stress, manufacturing, and product organizations to assess technology readiness, mitigate reliability risks, and drive continuous improvements in reliability and product quality. In this role, you will help drive technology certification and defect reduction by working across organizations to identify reliability risks, evaluate technology readiness, and develop solutions that enable successful technology development and high-volume manufacturing. You will contribute to advancing integrated reliability methodologies, defect reliability assessments, technology certification frameworks, and MTS quality systems supporting Intel Foundry's advanced technology portfolio. Responsibilities may include but are not limited to: • Developing and executing integrated and defect reliability certification strategies for advanced semiconductor process technologies, including qualification requirements, certification methodologies, acceptance criteria, and technology health metrics. • Driving technology certification activities, including HTOL, ELFR, ELF modeling, defect reliability process controls, screening methodologies, and related reliability assessments. • Designing and executing experiments to characterize reliability behavior, validate reliability models, and understand device and process failure mechanisms. • Developing reliability risk assessments and providing data-driven recommendations for technology readiness and certification decisions. • Building and applying statistical models to assess defectivity, latent reliability risk, and product quality. • Collaborating with process integration, design, device, manufacturing, and product teams to identify and resolve technology reliability challenges. • Driving statistical quality methodologies, including process capability analysis, MTS, CPK, and process monitoring systems. • Developing automation, data analytics, and AI-assisted solutions to improve engineering productivity and technical decision making. • Communicating technical findings, recommendations, certification status, and risks to engineering and management stakeholders.
Additional qualifications include: • Strong analytical and problem-solving skills. • Knowledge of semiconductor device physics and manufacturing fundamentals. • Experience with statistical analysis and experimental design. • Excellent written and verbal communication skills. • Ability to work effectively in a highly collaborative and cross-functional environment.
Minimum Qualifications The candidate must possess a Ph.D. degree in Electrical Engineering, Materials Science, Physics, Reliability Engineering, Semiconductor Engineering, or a related technical discipline. At least 2 years of experience in Semiconductor industry.
Preferred Qualifications: Experience in one or more of the following areas: • Semiconductor reliability engineering and technology qualification. • Advanced CMOS technology development and process integration. • Defect reliability, latent defect modeling, and reliability statistics. • HTOL, ELFR, TDDB, BTI, HCI, electromigration, or related reliability mechanisms. • Product and technology qualification methodologies. • Semiconductor failure analysis and physical characterization techniques. • Statistical quality systems, process capability analysis, MTS, and CPK methodologies. • Design of Experiments (DOE), JMP, SAS, R, or equivalent analytical tools. • Data analytics, machine learning, and automation using Python, SQL, or similar programming languages. • AI-assisted data analysis and engineering workflow automation.
Experienced Hire
Shift 1 (United States of America)
US, Oregon, Hillsboro
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $155,520.00-219,550.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.