Intel
India, Bangalore
Standalone drives and builds functional Emulation model environment using graphics logic components, including 3D graphics, media for various media IP's, Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design builds. works with different EDA vendors to enhance emulation model builds.
Minimum Qualifications:
• Master's degree in a relevant field (e.g., Electronics, Computer Science, Embedded Systems) with 8-15 years of hands-on experience in pre- silicon Emulation model builds using different vendor platforms. • Knowledge of emulation model builds and releases and/or ability to perform analysis on the emulation model performance and size. Ability to experiment with various techniques and solutions to reduce model size in situations where RTL constructs lead to unwanted size increase such memory structure implemented as registers • Knowledge of and ability to use emulators (e.g., ZeBu, Palladium, Veloce or FPGA) that create and run virtual machines to develop and implement test plans, create test scenarios, and validate IPs/SoCs on emulation platforms. Ability to use emulation software suites including Maestro, Metro-Maestro, and Supercollider. • Ability to understand what emulation is, differences between emulation and other pre-silicon platforms, procs and cons, various usages, and latest emulation industry trend. Ability to use emulation models for RTL verification, FW-HW co-verification, and performance validation. • Knowledge of emulation model builds and releases and/or ability to perform analysis on the emulation model performance and size. Ability to experiment with various techniques and solutions to reduce model size in situations where RTL constructs lead to unwanted size increase such memory structure implemented as registers. • Ability to design, develop, understand, and optimize test environments such as stress stimuli and trackers to validate and verify products, components, and systems. • Ability to architect and implement an IP test environment (checkers, monitors, test infrastructure, VC) to meet the requirements of IP/SoC including expertise in Verdi, VCS, and UVM/OVM • Knowledge of digital basic building blocks (including combinatorial/sequential design, finite state machines, registers, counters), • Ability to make commitments through clear, prioritized goals and high-quality decisions, assume responsibility for outcomes, and predictably execute and meet those commitments over time. Ability to overcome challenges, recover from setbacks, and adapt and adjust course as needed based on data to achieve desired results for the team, customers, and Intel. Consistently uses Intel's enterprise standards for goal setting, decision making, and meeting practices to move work forward rapidly and effectively. • Knowledge of tools and flows used to validate an IP and handoff to SoC. • Ability to identify and diagnose a problem, to propose, implement, and test solutions, and to drive effective and sustainable solutions across unique situations. • Knowledge of validation processes including HSD-ES, DCCB (APM), and Gatekeeper management. • Working knowledge of scripting languages, including Python, Perl, or Ruby. • Demonstrated problem-solving, debugging, and technical analysis skills. Preferred Qualifications:
Experienced Hire
Shift 1 (India)
India, Bangalore
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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